Job Description

FPGA Design Verification Engineer Supporting Next-Gen Radar & Avionics Systems for a Top Aerospace & Defense Client in the Country

We are seeking a skilled FPGA Design Verification Engineer to join our dynamic team. This role involves the design verification of VHDL for FPGA, including DV planning, testbench infrastructure creation, testcase development, testing, debugging, and coverage closure. The successful candidate will develop all DV code using SystemVerilog/UVM, adhering to industry best practices.

*No clearance required, but must be eligible to obtain one!

Responsibilities

  • Create coverage and verification plan documents detailing verification flows, functionality to be verified, and testbench usage.
  • Develop a Work Breakdown Structure (WBS), Gantt charts, and plans showing task breakdown, duration estimates, milestones, and task assignments.
  • Build SV/UVM testbench infrastructure, including environment...

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