FPGA IO Front End Design Engineer

Altera .FPGA IO Front End Design Engineer page is loaded## FPGA IO Front End Design Engineerlocations: Penang 15, Penang, Malaysiatime type: Full timeposted on: Posted Todayjob requisition id: R01961# **Job Details:**### ## **Job Description:*** As an FPGA IO Front End Design Engineer, you will be responsible to define & implement the design (micro-architecture, BMOD/RTL, linting, CDC, SDC, UPF/power gating) of high speed IO design in cutting edge technology node.* You will work closely with verification team for design test plan and validation review and back-end team for floor planning, physical implementation, STA timing closure. You will need to work on post Silicon debug/characterization support of the designs.### ## **Qualifications:*** BS/MS or PhD in Electronics Engineering with minimum of 5 years of IO Front End frontend experience* Strong in communication, leadership, investigation, problem solving & analytical skill* Proficiency with RTL coding using HDL language(s)...