Job Description

We are hiring an engineer with strong FPGA RTL fundamentals and scripting expertise to work on FPGA design tool validation and flow testing. This role focuses on validating FPGA tools and flows rather than silicon RTL development or hardware testing.
Job Description:
- Write and review RTL code using Verilog, System Verilog, or VHDL to enable FPGA tool and flow validation
- Validate FPGA design and synthesis flows, leveraging strong logic and digital design fundamentals
- Perform Vivado synthesis and flow testing, analyzing tool behavior across stages
- Apply solid understanding of Xilinx FPGA architecture to create meaningful validation scenarios
- Develop Tcl and Python scripts to automate test cases, execution, and result analysis
- Work closely with internal teams to debug tool-related issues and improve validation coverage
If you’re looking to build deep expertise in FPGA flows and EDA tool behavior, this role offers strong technical exposure and long-term growth.
Thanks,
Karthik Kumar

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