Job Description


Job Description:

Pay Range: $90hr - $125hr
  • We are seeking an experienced FPGA/VHDL Design Engineer to develop and implement complex algorithms targeting ASICs and FPGAs.
  • The ideal candidate will be proficient in VHDL and have hands-on experience with Xilinx FPGAs and the Vivado design suite.
  • This is a mid to senior-level role requiring expertise in architecture, design, verification, synthesis, and static timing analysis.
  • Prior exposure to high-speed communication protocols and embedded software is a plus.
    • Requirement/Must Have:
  • At least 3 years of experience implementing complex algorithms on ASIC/FPGAs
  • Proficiency in VHDL with 5+ years of hands-on experience
  • Hands-on experience with Xilinx FPGA design using Vivado
  • Experience with complete FPGA design cycle: architecture, design, verification, synthesis, and static timing analysis (STA)
  • Strong analytical and de...

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