Job Description
Responsibilities
Design architecting and trade-off analysisRTL coding and verificationMemory Controller + PHY integration and verificationCustomer delivery and supportQualifications
Strong System Verilog/Verilog RTL design expertise
Questa/Incisive/VCS simulator experiencePython/Perl/Tcl scripting experienceSignificant ASIC and/or FPGA design experienceAbility to learn quickly and work independentlySolid communication and project management skills5+ years of logic design experienceBSEEDefinite Plus:
ASIC synthesis, timing constraint, CDC/RDC experienceVerification experienceMemory (HBM, GDDR, LPDDR, DDR) expertiseAMBA AXI or CHI design experienceLocated in the Hillsboro, Oregon areaTraining:
Provided as needed
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