Job Description
Emulation Engineer
Experience : 4-5 years
Location : Hyderabad
4-5 yrs of experience in emulation/prototyping using Cadence/Synopsys tool flows (Palladium/Protium/HAPS/Zebu)
Working knowledge of System Verilog & Verilog language semantics and compilation flows
Solid understanding on SOC architecture and AXI protocol
Good communication skills and team collaboration
Interested,please share your updated resume to [email protected]
Apply for this Position
Ready to join ACL Digital? Click the button below to submit your application.
Submit Application