Job Description
Job Description1. Focus on high-speed SerDes IP design, including the development of PCIe/USB, IC functional verification, and system performance improvement.
2. Collaborate with analog/digital/algorithm design teams to develop chips from prototype design to mass production.
3. Responsible for implementing algorithms and related PHY Link training control flow design.
4. Assist in establishing simulation models during the design phase to increase verification coverage, achieve automated verification of high-speed interfaces, debug, and support IP integration into products and customer applications.
#LI-DC3
Requirement1. Master's degree in electrical engineering, communication, or equivalent.
2. Familiar with PCIe/USB standards at different definition layers (one or more), including Physical Layer (Electrical specification)/Link layer/Protocol layer.
3. Experience in PCIe Gen4/USB3 or above verification, and hands-on experience with LTSSM operation functi...
2. Collaborate with analog/digital/algorithm design teams to develop chips from prototype design to mass production.
3. Responsible for implementing algorithms and related PHY Link training control flow design.
4. Assist in establishing simulation models during the design phase to increase verification coverage, achieve automated verification of high-speed interfaces, debug, and support IP integration into products and customer applications.
#LI-DC3
Requirement1. Master's degree in electrical engineering, communication, or equivalent.
2. Familiar with PCIe/USB standards at different definition layers (one or more), including Physical Layer (Electrical specification)/Link layer/Protocol layer.
3. Experience in PCIe Gen4/USB3 or above verification, and hands-on experience with LTSSM operation functi...
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