Layout Design, Sr Staff Engineer

• Lead and execute Analog Mixed-Signal layout design for high-speed DDR/HBM IPs
• Deliver robust and high-quality physical layout designs ensuring adherence to DDR/HBM specs
• Apply deep understanding of FinFET and CMOS technology at 28nm and below
• Handle high-speed digital layout verification with attention to signal integrity
• Implement advanced floorplanning techniques and apply submicron mitigation strategies
• Coordinate with remote layout teams globally for layout quality and deliverables
• Drive internal flow adherence for tape-out readiness and schedule compliance
• Collaborate with PHY designers, package engineers, and system teams to meet design objectives
• Oversee IO layout requirements including bondpads, ESD, IR/EM, and DFM considerations
• Utilize physical verification tools and support Place & Route and top-level verification flows

The Impact You Will Have:

• Shape next-...