Lead Application Engineer

Lead Application Engineer – Cadence

Location: Tampere, Finland
Reports to: AE Director

Job Overview

This Digital IC design and support role offers an opportunity to work on a variety of digital implementation and support activities associated with Cadence EDA tools for Synthesis, Logical Equivalency Checking (LEC), Design-for-Test (DFT), Place & Route and Static Timing Analysis (STA). You may get involved in design services projects and/or supporting customers using Cadence tools on their projects in areas such as 5G, IOT, automotive, advanced CPU, wireless, audio, image processing, AI, machine learning etc.

This role is ideal for someone with several years of hands on ASIC/IC design experience who is looking for a new challenge in an absorbing customer facing role. This role requires strong technical capability in Cadence tools (or similar), flow development, and the ability to think outside the box.

Job Responsibilities

• Support customers using Cadence EDA software in areas such as Synthesis, DFT, Logical Equivalency Checking, Low Power Design Implementation, SDC Verification, Place and Route, Parasitic Extraction, Timing Signoff, Power Signoff
• Be the primary focal point for technical issues, questions, and discussions for a given customer engagement
• Lead technical discussions with customers and serve as the primary technical interface between customer and Cadence R&D
• Develop an understanding of the customer's needs and of the competition's technology and sales strategies
• Perform methodology assessments, improve existing design methodologies, and develop new ones that leverage Cadence technology and services
• Create and conduct technical presentations and product demonstrations to customers
• Perform on-site visits and some travel as required
• Mentor other AEs and collaborate effectively within the team
• Review, document, and resolve project technical issues; escalation of issues to Project Management when appropriate

Job Qualifications

• MS in Electronics Engineering with minimum 5+ years industry related experience in design and/or EDA
• 4+ years of experience with Synthesis (Genus or Design Compiler), DFT and Logic Equivalency tools or Cadence or Synopsys place and route tools (Physical Synthesis, PnR, CTS, Static Timing Analysis)
• Experience diagnosing and resolving complicated PPA, Low Power implementation and TAT issues
• Exceptional troubleshooting and analytical skills
• Excellent command in scripting languages such as Perl, Tcl and shell scripting essentials
• Strong problem solving & analysis skills covering digital implementation
• Proven track record and experience working in a fast‑paced environment
• Excellent customer interaction & presentation skills

Equal Employment Opportunity

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

Seniority Level

Mid‑Senior level

Employment Type

Full‑time

Job Function

Engineering and Information Technology – Software Development