Job Description
We are looking for a Senior / Principal ASIC Design Verification Engineer to lead hands-on verification of complex So Cs or large subsystems, owning execution from verification planning through tapeout and silicon correlation. This role requires deep UVM expertise and strong closure discipline.
Job Description:
Own end-to-end verification at subsystem or So C level, including authoring verification plans from specs and micro-architecture and building reusable UVM/System Verilog environments from scratch.
Develop constrained-random and directed tests, scoreboards, checkers, coverage models, and SVA assertions to ensure functional correctness.
Drive functional, code, and assertion coverage closure, debug complex failures, and collaborate closely with RTL, architecture, and DFT teams.
Enable So C-level verification covering IP/interface integration, coherency, low-power modes, resets/boot flows, and performance validation.
Verify standard interfaces and complex subsystems such as AXI/ACE, DDR/PCIe, coherency fabrics, memory and interrupt subsystems, and power states.
Support silicon bring-up and post-silicon correlation, leveraging scripting (Python/Tcl) and low-power or emulation exposure as value adds.
If you’re seeking ownership of verification closure for silicon-critical designs and the opportunity to influence real So C quality from pre-silicon to post-silicon, this role offers strong technical depth and impact.
Thanks,
Girish Nidyamale
Job Description:
Own end-to-end verification at subsystem or So C level, including authoring verification plans from specs and micro-architecture and building reusable UVM/System Verilog environments from scratch.
Develop constrained-random and directed tests, scoreboards, checkers, coverage models, and SVA assertions to ensure functional correctness.
Drive functional, code, and assertion coverage closure, debug complex failures, and collaborate closely with RTL, architecture, and DFT teams.
Enable So C-level verification covering IP/interface integration, coherency, low-power modes, resets/boot flows, and performance validation.
Verify standard interfaces and complex subsystems such as AXI/ACE, DDR/PCIe, coherency fabrics, memory and interrupt subsystems, and power states.
Support silicon bring-up and post-silicon correlation, leveraging scripting (Python/Tcl) and low-power or emulation exposure as value adds.
If you’re seeking ownership of verification closure for silicon-critical designs and the opportunity to influence real So C quality from pre-silicon to post-silicon, this role offers strong technical depth and impact.
Thanks,
Girish Nidyamale
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