Lead Debug/Trace/Profiling Design Engineer

Lead Debug/Trace/Profiling Design Engineer – SiFive, Cambridge, England, United Kingdom

SiFive is seeking a hardware design technical lead who is passionate about designing industry-leading debug, trace and profiling IP to help drive the tidal wave of adoption of RISC‑V as the architecture of choice for SOC designs across a broad variety of vertical applications.

Job Description

We build and maintain our RISC‑V processor subsystem IP using the Chisel hardware construction library embedded in the Scala language and are seeking a motivated individual to lead enhancement of our existing debug/trace/profiling hardware as well as development of new capabilities in this area. Opportunities exist to engage with customers, partners and tools vendors to help determine the future of the debug, trace and profiling solutions, as well as opportunities to engage with the RISC‑V International Association to help drive the state of the art of debug strategy.

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