Job Description

Location:

Bangalore or Hyderabad
Full time position supporting our customer onsite

A Lead DFT (Design for Test) Engineer drives the architecture, implementation, and verification of test features (Scan, MBIST, IJTAG) for complex, high-performance SoCs.

Responsibilities include managing pre-silicon DFT insertion, ATPG pattern generation, and post-silicon validation/debug on ATE to ensure high-quality, cost-effective manufacturing tests.
Key Responsibilities
DFT Architecture & Design:

Define and implement DFT structures for complex IP, including processors, AI engines, and high-speed controllers.
Methodology & Flow:

Drive Scan insertion, MBIST/LBIST, Boundary Scan (JTAG), and iJTAG/IEEE1687 integration.
ATPG & Verification:

Generate, simulate, and verify high-quality manufacturing test patterns (Stuck-at, Transition, Path-Delay) for maximum coverage.
Silicon Bring-up & Debug:

Work with product/yield engineer...

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