Job Description
Lead SoC Verification Engineer Experience: 8+ Years
Location: Bengaluru, India
Role Overview
We are looking for a Lead SoC Verification Engineer with 8+ years of experience to drive functional verification of complex SoC designs. The ideal candidate will lead the verification strategy, mentor junior engineers, and collaborate closely with design and architecture teams to ensure high-quality silicon delivery.
Key Responsibilities
Lead SoC-level and IP-level verification for complex digital designs
Define and own verification plans, methodologies, and coverage goals
Develop and maintain SystemVerilog / UVM-based verification environments
Drive testbench architecture , stimulus generation, and checkers
Ensure functional, code, and assertion coverage closure
Debug and analyze functional failures across RTL, testbench, and system level
Collaborate with RTL design, architecture, DFT, and post-silicon teams
Review verification deliverables and enforce best practices
Mentor and technically guide junior verification engineers
Support regression, gate-level simulations, and sign-off activities
Required Qualifications
8+ years of experience in SoC / ASIC functional verification
Strong expertise in SystemVerilog and UVM methodology
Hands-on experience with SoC verification , including:
Multiple IP integrations
Interconnects (AXI/AHB/APB)
Power-aware verification (UPF/CPF – good to have)
Strong knowledge of coverage-driven verification
Experience with assertion-based verification (SVA)
Proficiency in debugging using simulators (VCS, Xcelium, Questa)
Solid understanding of RTL design concepts and SoC architecture
Scripting experience in Python / Perl / Shell
Good to Have
Experience with Formal Verification
Exposure to Low-power verification
Experience with Gate-Level Simulation (GLS)
Knowledge of post-silicon validation/debug
Prior experience in leading or mentoring teams
Education
B.Tech / M.Tech in Electronics, Electrical, or related discipline
About Us:
Silicon Patterns is a specialized engineering services company with deep expertise in pre-silicon and post-silicon design and verification. We deliver end-to-end semiconductor and embedded system solutions covering RTL Design, SystemC Modeling, Emulation, Design Verification (DV), Physical Design (PD), Design for Testability (DFT), and Pre- & Post-silicon Validation — helping clients achieve faster, more reliable product development. Headquartered in Hyderabad, with offices in Bangalore and Raipur, and supported by our skilled engineering teams in Malaysia, we serve global clients through flexible engagement models like Time & Materials (T&M), Offshore Development Centers (ODC), Subcontracting, and Build-Operate-Transfer (BOT). Our expertise spans VLSI and Embedded Systems, with a strong focus on Wireless, IoT, and Automotive domains. We also work on advanced technologies including HBM3/3E workloads, AI/ML, GenAI/LLMs, and edge computing. At Silicon Patterns, we’re committed not only to technical excellence but also to maintaining a strong work-life balance for our teams because great engineering starts with well-supported people.
Website
Location: Bengaluru, India
Role Overview
We are looking for a Lead SoC Verification Engineer with 8+ years of experience to drive functional verification of complex SoC designs. The ideal candidate will lead the verification strategy, mentor junior engineers, and collaborate closely with design and architecture teams to ensure high-quality silicon delivery.
Key Responsibilities
Lead SoC-level and IP-level verification for complex digital designs
Define and own verification plans, methodologies, and coverage goals
Develop and maintain SystemVerilog / UVM-based verification environments
Drive testbench architecture , stimulus generation, and checkers
Ensure functional, code, and assertion coverage closure
Debug and analyze functional failures across RTL, testbench, and system level
Collaborate with RTL design, architecture, DFT, and post-silicon teams
Review verification deliverables and enforce best practices
Mentor and technically guide junior verification engineers
Support regression, gate-level simulations, and sign-off activities
Required Qualifications
8+ years of experience in SoC / ASIC functional verification
Strong expertise in SystemVerilog and UVM methodology
Hands-on experience with SoC verification , including:
Multiple IP integrations
Interconnects (AXI/AHB/APB)
Power-aware verification (UPF/CPF – good to have)
Strong knowledge of coverage-driven verification
Experience with assertion-based verification (SVA)
Proficiency in debugging using simulators (VCS, Xcelium, Questa)
Solid understanding of RTL design concepts and SoC architecture
Scripting experience in Python / Perl / Shell
Good to Have
Experience with Formal Verification
Exposure to Low-power verification
Experience with Gate-Level Simulation (GLS)
Knowledge of post-silicon validation/debug
Prior experience in leading or mentoring teams
Education
B.Tech / M.Tech in Electronics, Electrical, or related discipline
About Us:
Silicon Patterns is a specialized engineering services company with deep expertise in pre-silicon and post-silicon design and verification. We deliver end-to-end semiconductor and embedded system solutions covering RTL Design, SystemC Modeling, Emulation, Design Verification (DV), Physical Design (PD), Design for Testability (DFT), and Pre- & Post-silicon Validation — helping clients achieve faster, more reliable product development. Headquartered in Hyderabad, with offices in Bangalore and Raipur, and supported by our skilled engineering teams in Malaysia, we serve global clients through flexible engagement models like Time & Materials (T&M), Offshore Development Centers (ODC), Subcontracting, and Build-Operate-Transfer (BOT). Our expertise spans VLSI and Embedded Systems, with a strong focus on Wireless, IoT, and Automotive domains. We also work on advanced technologies including HBM3/3E workloads, AI/ML, GenAI/LLMs, and edge computing. At Silicon Patterns, we’re committed not only to technical excellence but also to maintaining a strong work-life balance for our teams because great engineering starts with well-supported people.
Website
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