Lead System Verification Engineer

Role: Lead Design Verification

Experience: 7 to 10 years

Notice Period: Immediate to 15 days

Location: Bengaluru

KEY RESPONSIBILITIES:

• Understanding Ips like (PCIE)
• IP deployment to complex SOCs and get the integration testing done.
• Testcase coding, Debugging issues, regressions, UVM agent coding, checkers coding, scoreboard coding and Assertions coding.

PREFERRED EXPERIENCE:

• Knowledge of High speed peripheral (PCIE)
• Expertise in IP, Subsystem and SOC Verification with specialization in Integration, verification tools
• Strong hands-on experience in different SOC Verification activities, UVM, System Verilog, kv, X86, C++, HW/SW co-verification, Test plan review, Debug/triage, Coverage, Strong Problem Solving, Automation and Debugging Skills, System bus protocol understanding including some of the common IPs like ACE, CHI, AXI, PCIe, DDR, memory controller etc.
• Comfortable with design/verification tools and flows like VCS, Verdi, SOC Connectivity, SV assertions, HW-SW co-simulations, UPF/CPF flows etc.
• Strong understanding of System integration, Make file flow, Verification Methodologies, Boot up sequence.
• JIRA based project management is a plus.

If Interested please share your profile at my email id [email protected]