Memory Cell Test Structure Engineer - Layout & Verification

A global leader in memory solutions in Jalisco is seeking an experienced professional to develop memory cell-based test structures and support several teams. The ideal candidate must possess a Bachelor’s in Electrical or Microelectronic Engineering with at least 5 years of experience, particularly in EDA tools like Cadence Virtuoso and Calibre. This role involves problem-solving, circuit design, and collaboration across multiple departments to enhance product quality and innovation. #J-18808-Ljbffr