Memory Sub-System Validation Engineer - Data Center GPU

Overview

Memory Sub-System Validation Engineer – Data Center GPU

Location: Markham, Canada

The role involves pre- and post-silicon validation and characterization of memory sub-systems on AMD’s Datacenter GPU (Machine Instinct product). The candidate will drive validation efforts across memory technologies, interfacing with DRAM architecture & product engineering, Memory Controller Design and Software, and DDR PHY to ensure delivery from architecture to mass production in line with AMD quality and industry standards.

What You Do

The Datacenter Graphics and Accelerated Computing Validation Team is seeking a dynamic and energetic individual to join our post-silicon validation effort. The High-Bandwidth Memory (HBM) sub-system delivers industry-leading Datacenter solutions for Machine Learning (ML) and High-Performance Computing (HPC). You will be a key interface for validating on-die HBM or off-die DDR memory, contributing to the validation strategy and execution to support AMD’s Datacenter GPU products.

Key Responsibilities

• Memory Sub-system Validation Engineer’s responsibility includes all aspects of pre- and post-silicon validation from planning, execution and debug.
• Develop and execute test plans for HBM functional and electrical validation (PVT Shmoo characterization).
• Apply extensive knowledge of high-bandwidth memory subsystems, including SoC memory architecture, unified memory controller, PHY design and high-speed I/O interfaces, DRAM devices, and calibration/training mechanisms.

Key Qualifications

• Ability to apply knowledge of other high-speed, high-performance memory technologies.
• Experience working with major DRAM memory vendors and validation of DRAM devices is a plus.
• Debug skills to root-cause post-production issues and customer returns.
• Proven ability to drive resolution of critical problems; comfortable working in a lab environment.

Preferred Experience

• Significant experience in SoC validation, verification and debug of High-Bandwidth Memory sub-system.
• Develop functional and electrical validation plans for memory features; align cross-functional teams on support and validation plans.
• Drive debug in post-silicon, root-cause problems and steer the team to corrective actions.
• Collaborate across Design, Verification, Silicon Validation, Productization, System Hardware and Software teams on memory-related silicon issues.
• Hands-on experience with JTAG, I2C, test equipment and lab tools.
• Strong programming skills (C/C++, Python) and comfort with Linux or Windows.
• Experience in developing test cases for Machine Learning and High Performance Computing workloads.
• Ability to work effectively in a dynamic, multi-project environment.

Academic Credentials

• Bachelors or Masters in Electrical or Computer Engineering.

Compensation

Base pay range: $96,800.00/yr - $145,200.00/yr

Additional Information

Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Seniority level

• Mid-Senior level

Employment type

• Full-time

Job function

• Engineering and Information Technology

Industries

• Semiconductor Manufacturing

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