Memory Subsystem Verification Engineer (SystemVerilog/UVM)

A leading semiconductor company in Markham, Canada is seeking a Verification Engineer for their Memory Subsystem team. In this role, you will design and implement advanced verification environments using System Verilog and UVM methodologies. You will collaborate with cross-functional teams, develop test benches, and ensure comprehensive coverage of memory subsystem solutions. The ideal candidate has strong skills in C/C++, IP verification, and debugging co-verification environments. This position offers opportunities for career advancement and innovation in a collaborative culture.
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