Noc/ip-design verification lead engineer

Exp: 8+ Years
Location: Bangalore
JD:
Key Responsibilities:
· Develop UVM-based verification environments for No C/IP blocks such as Flex No C, GNOC, or custom No C fabrics.
· Define and implement test plans, coverage models, scoreboards, monitors, and checkers for coherent and non-coherent traffic.
· Integrate and verify IPs like AXI4, CHI-B/C/E, PCIe, and UCIe connected via No C.
· Model and validate credit-based flow control, packet routing, Qo S, and virtual channel behavior.
· Perform assertion-based verification (SVA/DVL) for protocol compliance and corner cases.
· Debug complex interactions at simulation or emulation level, including deadlocks, congestion, or ordering violations.
· Work closely with architects and RTL teams to align verification coverage and performance metrics.
· Perform coverage closure (code + functional) and ensure complete verification sign-off.
Required Skills:
· Strong experience with System Verilog, UVM, and object-...