Job Description
Qualcomm India Private Limited
Role Overview
The NPU Synthesis Lead will be responsible for driving synthesis and timing closure for Neural Processing Unit (NPU) IP and subsystems in cutting-edge SoCs. This role involves leading synthesis flows, optimizing for PPA (Performance, Power, Area), and collaborating with architecture, RTL, and physical design teams to ensure high-quality netlists for advanced technology nodes.
Key Responsibilities
- Synthesis Ownership
- Lead RTL-to-gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler, Cadence Genus).
- Develop and maintain synthesis scripts and flows for hierarchical and flat designs.
- Timing Closure
- Drive pre-layout and post-layout timing closure across multiple voltage and process corners.
- Collaborate with STA teams to resolve setup/hold violations.
- Power & Area Optimization
- Apply physical-aware synthesis techniques to meet aggressive PPA targets.
Role Overview
The NPU Synthesis Lead will be responsible for driving synthesis and timing closure for Neural Processing Unit (NPU) IP and subsystems in cutting-edge SoCs. This role involves leading synthesis flows, optimizing for PPA (Performance, Power, Area), and collaborating with architecture, RTL, and physical design teams to ensure high-quality netlists for advanced technology nodes.
Key Responsibilities
- Synthesis Ownership
- Lead RTL-to-gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler, Cadence Genus).
- Develop and maintain synthesis scripts and flows for hierarchical and flat designs.
- Timing Closure
- Drive pre-layout and post-layout timing closure across multiple voltage and process corners.
- Collaborate with STA teams to resolve setup/hold violations.
- Power & Area Optimization
- Apply physical-aware synthesis techniques to meet aggressive PPA targets.
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