Job Description
Hiring: NPU Synthesis Lead — Bangalore (15+ yrs)
We’re looking for an experienced NPU Synthesis Lead to drive RTL→Synthesis→Timing closure for NPU IP/subsystems in advanced SoCs, optimize PPA, and partner closely with RTL/STA/PD teams to deliver high‑quality netlists on cutting‑edge nodes.
📧 Queries: [email protected]
Key Responsibilities
- Own RTL‑to‑gate synthesis for NPU IP/subsystems; build & maintain synthesis scripts/flows
- Lead pre‑/post‑layout timing closure across corners; partner with STA to resolve setup/hold
- Drive physical‑aware synthesis and low‑power strategies (UPF/CPF) for aggressive PPA targets
- Manage SDC constraints (clocks, I/O, MCP, false paths)
- Perform LEC, CLP, lint, and flow QoR checks; mentor junior engineers
Mandatory Skills (Must‑Have)
- 15+ years in ASIC synthesis & timing closure; 3+ years with NPU/AI/DSP cores
- Strong ASIC flow knowledge: RTL → Synthesis → STA → P&R
- Hands‑on with Synopsys Design Compiler / ...
We’re looking for an experienced NPU Synthesis Lead to drive RTL→Synthesis→Timing closure for NPU IP/subsystems in advanced SoCs, optimize PPA, and partner closely with RTL/STA/PD teams to deliver high‑quality netlists on cutting‑edge nodes.
📧 Queries: [email protected]
Key Responsibilities
- Own RTL‑to‑gate synthesis for NPU IP/subsystems; build & maintain synthesis scripts/flows
- Lead pre‑/post‑layout timing closure across corners; partner with STA to resolve setup/hold
- Drive physical‑aware synthesis and low‑power strategies (UPF/CPF) for aggressive PPA targets
- Manage SDC constraints (clocks, I/O, MCP, false paths)
- Perform LEC, CLP, lint, and flow QoR checks; mentor junior engineers
Mandatory Skills (Must‑Have)
- 15+ years in ASIC synthesis & timing closure; 3+ years with NPU/AI/DSP cores
- Strong ASIC flow knowledge: RTL → Synthesis → STA → P&R
- Hands‑on with Synopsys Design Compiler / ...
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