PD engineer

• Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs.
• Define and drive physical design strategies to meet aggressive performance, power, and area targets.
• Conduct detailed analysis of timing, power, and area, and drive design optimizations to improve QoR.
• Block/Partition signoff closure for STA, PV, LEC, IR/EM, CLP very efficiently.
• Provide technical leadership and guidance to the physical design team, mentoring junior engineers and fostering a culture of excellence.
• Work closely with RTL design and DFT teams to understand design requirements and constraints, and drive successful tapout of designs.
• Support and Development of advanced physical design methodologies and flows for complex semiconductor designs.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering or Electronics & Communications.
• 4.5+ years of experience ...