Job Description
Minimum qualifications:
- Bachelor's degree in Mechanical Engineering, Electrical Engineering, Industrial Engineering or equivalent practical experience
- 5 years of experience in ASIC physical design flows and methodologies in advanced process nodes.
- Experience in synthesis, PnR and sign-off optimizations, sign-off convergence, including Static Timing Analysis (STA), electrical checks and physical verification.
- Experience in one or more of synthesis/PnR tools (e.g., Genus, Innovus, DC and ICC, STA tools).
- Bachelor's or Master's degree in Computer Science, or a related technical field.
- 3 years of experience in ASIC physical design flows with strong emphasis on physical verification convergence and tapeout signoff.
- Experience in engineering across physical design and top-level implementation.
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