Physical Design Engineer

Senior Physical Design Engineer

Location: Bangalore

Experience: 5+ Years

Key Responsibilities:

• SoC top-level and block-level physical implementation (Synthesis, P&R, STA, signoff)
• Timing closure for complex blocks and full-chip designs
• Top-level floorplanning, clock planning, and high-speed signal planning
• CTS debug (HTREE/MSCTS) and skew/latency optimization
• PPA optimization (Power, Performance, Area)
• SDC cleanup, synthesis optimization, low-power checks, and LEC
• Debug LVS/DRC issues at block and chip level
• Work on advanced nodes (8nm/5nm/4nm) and large SoCs (>20M gates, >1GHz)
• Hands-on with tools: ICC, DC, PrimeTime, RedHawk, Calibre, Formality
• Scripting using Tcl/Perl
• Experience with multiple voltage/clock domains and SoC tape-outs preferred

Nice to Have:

• Sub-system / SoC top commit experience
• Recent successful SoC tape-outs
• CHBM exposure

Interested candidates can apply or DM for details.