Physical Design Engineer

About us:

Sasken is a pioneer in Product Engineering and Digital Transformation delivering concept-to-market and chip-to-cognition R&D solutions to customers across the semiconductor, automotive, industrial, consumer electronics, enterprise devices, satellite communications, telecom, and transportation domains. Through the last three decades, Sasken’s deep engineering capabilities and technology patents have helped transform over a hundred Fortune 500 clients and powered more than a billion digital devices from its state-of-the-art facilities in India, Finland, Germany, and Japan. Sasken has always been at the forefront of technology in the cellular modem, radio access network, and satellite domains, more recently delivering state-of-the-art solutions to its automotive Tier 1 and OEM customers in the IVI, Body Electronics, Instrument Cluster, ADAS, and Autonomous vehicles, V2X, and Telematics domains. Sasken’s investments in technology and innovation have continued to benefit its customers. Sasken has been listed on the NSE and BSE, Mumbai, India, since 2005

We are seeking a highly skilled Physical Design Engineer with over 6 years of industry experience.

The ideal candidate will have proven expertise as an individual contributor across multiple projects,

with strong hands-on skills in RTL-to-GDSII implementation flow. Experience working on advanced

technology nodes such as TSMC N3, N5, and 12nm is a must.

Key Responsibilities

• Drive the RTL-to-GDSII flow including synthesis, floorplanning, placement, CTS, routing, and

sign-off.

• Perform timing closure, power optimization, and area optimization at block and chip level.

• Handle physical verification (DRC, LVS, ERC) and ensure design quality meets foundry

requirements.

• Collaborate with RTL designers, verification engineers, and architecture teams to deliver

high-quality silicon.

• Work independently as an individual contributor across multiple complex projects.

• Ensure successful tape-out for advanced nodes (N3, N5, 12nm).

Required Skills & Experience

• 6+ years of hands-on experience in Physical Design.

• Strong expertise in RTL-to-GDSII flow.

• Proven track record of working on TSMC advanced nodes (N3, N5, 12nm).

• Proficiency in industry-standard EDA tools.

• Solid understanding of timing analysis, power analysis, and signal integrity.

• Experience in floorplanning, placement, CTS, routing, ECOs, and sign-off.

• Ability to work independently and deliver results under tight schedules.

Preferred Qualifications

• Experience in multi-million gate designs.

• Familiarity with low-power design techniques.

• Strong problem-solving and analytical skills.

• Excellent communication and collaboration abilities.

Why Join Us

• Opportunity to work on cutting-edge technology nodes.

• Be part of a world-class team delivering high-performance silicon.

• Competitive compensation and growth opportunities