Job Description
Join Our Team at e Infochips (An Arrow Company) as a Physical Design Engineer!
Location: Noida
Experience: 3+ Years
We are looking for skilled Physical Design Engineers to work on advanced So C and ASIC designs across cutting-edge technology domains.
Key Responsibilities:
Perform end-to-end Physical Design implementation including floorplanning, placement, CTS, routing, and signoff
Handle timing closure across multiple modes and corners
Run and analyze STA, IR drop, EM, and power integrity checks
Collaborate closely with RTL, DFT, and verification teams to resolve design issues
Support physical verification including DRC, LVS, and ANT checks
Debug and resolve timing, congestion, and signal integrity issues
Mandatory Skills & Experience:
✅ 3+ years of hands-on experience in ASIC Physical Design
✅ Strong knowledge of floorplanning, P&R, CTS, and timing closure
✅ Proficiency with industry-standard EDA tools (Synopsys/Cadence toolsets)
✅ Good understanding of low-power techniques (UPF/CPF)
✅ Experience with STA, IR/EM analysis, and physical verification flows
✅ Solid understanding of digital design and So C architecture
✅ Strong analytical, debugging, and communication skills
Why Choose e Infochips?
✨ Work on high-impact and advanced silicon projects
✨ Competitive compensation and comprehensive benefits
✨ Opportunity to grow in a global engineering organization
✨ Culture that values innovation, ownership, and continuous learning
Share your resume at:
Location: Noida
Experience: 3+ Years
We are looking for skilled Physical Design Engineers to work on advanced So C and ASIC designs across cutting-edge technology domains.
Key Responsibilities:
Perform end-to-end Physical Design implementation including floorplanning, placement, CTS, routing, and signoff
Handle timing closure across multiple modes and corners
Run and analyze STA, IR drop, EM, and power integrity checks
Collaborate closely with RTL, DFT, and verification teams to resolve design issues
Support physical verification including DRC, LVS, and ANT checks
Debug and resolve timing, congestion, and signal integrity issues
Mandatory Skills & Experience:
✅ 3+ years of hands-on experience in ASIC Physical Design
✅ Strong knowledge of floorplanning, P&R, CTS, and timing closure
✅ Proficiency with industry-standard EDA tools (Synopsys/Cadence toolsets)
✅ Good understanding of low-power techniques (UPF/CPF)
✅ Experience with STA, IR/EM analysis, and physical verification flows
✅ Solid understanding of digital design and So C architecture
✅ Strong analytical, debugging, and communication skills
Why Choose e Infochips?
✨ Work on high-impact and advanced silicon projects
✨ Competitive compensation and comprehensive benefits
✨ Opportunity to grow in a global engineering organization
✨ Culture that values innovation, ownership, and continuous learning
Share your resume at:
Apply for this Position
Ready to join ? Click the button below to submit your application.
Submit Application