Physical Design Engineer

We are seeking an adaptive, self‑motivated Physical Design Engineer to join our growing team. As a key contributor, you will help drive capabilities in delivering high‑performance, power‑efficient silicon solutions. The Physical Design team values continuous technical innovation and supports professional growth through challenging projects and collaborative success. In this role, you will be responsible for full‑chip floorplanning, physical implementation, timing closure, and power optimization across complex SoC designs.

KEY RESPONSIBILITIES

• Extensive hands‑on experience in floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification
• Proficient in timing and SDC constraint generation and management; strong debugging skills are a plus
• Solid understanding of low‑power design methodologies, including power‑aware synthesis and place‑and‑route; familiarity with voltage domain checks is advantageous