Job Description

  • 8 to 15 Years of Hands on Experience in Physical Design (Netlist to GDSII)
  • Proven experience in top level floorplanning/block partitioning, power planning
  • Understanding and planning of clock mesh structure/conventional CTS, Block integration (Including analog IP integration) and Physical Verification Signoff.
  • Engineer should have experience in handling chips of GHz clock frequency range & multi-million instance.
  • Should have designed complex chips in lower technology nodes (16nm and below).
  • Padframe/BGA planning/design, including RDL routing is required.
  • In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes.
  • Good exposure in Floorplanning, CTS, STA, Physical Verification, Basic understanding of timing constraints.
  • Good exposure to ICC2/Innovus/Calibre/Formality/LEC tool set.
  • Well versed in automation skills using shell/tcl/perl/python
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