Job Description

Job Description:

  • Lead end-to-end Physical Design flow from netlist to GDSII
  • Handle floorplanning, placement, CTS, routing, and sign-off
  • Work on advanced-node designs, TSMC 3nm (must-have)
  • Drive timing closure, congestion, power, and QoR improvements
  • Collaborate with STA, DFT, RTL, and sign-off teams
  • Review design quality and mentor junior engineers
  • Own block/chip-level delivery with minimal supervision

Mandatory Skills:

  • 7–10 years of hands-on Physical Design experience
  • Strong expertise in Cadence Innovus
  • Proven experience on TSMC 3nm technology
  • Solid understanding of timing, SI, IR/EM, and low-power design
  • Leadership experience (technical lead / mentoring / ownership)

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