Job Description

You are passionate about modern, complex processor architectures and bring deep expertise in physical implementation flows. You have experience in full-chip floorplanning, synthesis, place and route, timing closure, and power optimization. You are a collaborative team player with strong communication skills and a history of working across geographies and disciplines. You possess excellent analytical and problem-solving abilities, are eager to learn, and thrive in tackling complex design challenges.

Key Responsibilities

  • Extensive hands-on experience in floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification.
  • Proficient in timing and SDC constraint generation and management; strong debugging skills are a plus.
  • Solid understanding of low-power design methodologies, including power-aware synthesis and place-and-route; familiarity with voltage domain checks is advantageous.
  • Proven ex...

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