Physical Design Verification Professional

LTTS is looking for STA engineers with 5+ Years of experience, Detailed JD is mentioned below ::

- Good knowledge of timing closure knowledge for high frequency timing, congestion, and area sensitive designs.

- Can work closely with FE team for constraints development and constraints cleanup.

- Work with partitions/block owner to give timing ECO for timing closure.

- Knowledge of advanced timing closure techniques and methodology

- Knowledge of industry stanrd tools from Synops or Cadence.

- Worked on DSM technologies, tsmc 5nm and below experience preferred.

- Minimum 5+ of relevant experience

- Good scripting and communication skills