Job Description
Physical Verification Engineer
Experience: 2 to 5 Years
Location: Bangalore
Notice Period: Immediate
Job Description
Key Responsibilities:
Perform Physical Verification checks including DRC, LVS, ERC , and Antenna checks at block and full-chip level .
Work with foundry rule decks (TSMC / Samsung / GF / Intel / UMC etc.) to ensure design sign-off compliance.
Debug and resolve layout violations by working closely with the Physical Design, Layout, and Circuit teams.
Run Parasitic Extraction (PEX) and support timing and SI closure teams for accurate model generation.
Perform DFM checks and assist with design enhancements for manufacturability.
Support tape-out preparation , validation, reports, checklists, and documentation.
Required Skills & Expertise:
Strong working experience with Calibre / PVS / ICV for DRC & LVS sign-off.
Understanding of CMOS layout fundamentals, standard cells, macros, and routing architectures.
Familiari...
Experience: 2 to 5 Years
Location: Bangalore
Notice Period: Immediate
Job Description
Key Responsibilities:
Perform Physical Verification checks including DRC, LVS, ERC , and Antenna checks at block and full-chip level .
Work with foundry rule decks (TSMC / Samsung / GF / Intel / UMC etc.) to ensure design sign-off compliance.
Debug and resolve layout violations by working closely with the Physical Design, Layout, and Circuit teams.
Run Parasitic Extraction (PEX) and support timing and SI closure teams for accurate model generation.
Perform DFM checks and assist with design enhancements for manufacturability.
Support tape-out preparation , validation, reports, checklists, and documentation.
Required Skills & Expertise:
Strong working experience with Calibre / PVS / ICV for DRC & LVS sign-off.
Understanding of CMOS layout fundamentals, standard cells, macros, and routing architectures.
Familiari...
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