Job Description
Role: Post Silicon Validation Engineer(RTL Design, FPGA Design)
Experience: 5 – 8 years
Location: Hyderabad, On-site
Notice Period: Immediate Joiners
Responsibilities:
· FPGA Design Flow & Validation
· RTL Design, Implementation, and Protocols (PCIe, Ethernet, DDR4/5, Memory)
· ...
Experience: 5 – 8 years
Location: Hyderabad, On-site
Notice Period: Immediate Joiners
Responsibilities:
· FPGA Design Flow & Validation
· RTL Design, Implementation, and Protocols (PCIe, Ethernet, DDR4/5, Memory)
· ...
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