Power-Optimized Physical Design Lead for AI Chips

A leading technology company is looking for a Physical Design Engineer to optimize power for AI accelerator/GPU/APU chips. The role involves implementing advanced power optimization methodologies within the SOC project and enhancing existing methodologies. The ideal candidate will have background knowledge in digital ASIC design and physical design tools such as PTPX. They should possess strong teamwork and communication skills, with a degree in computer or electrical engineering. The position is hybrid and based in Markham, CA.
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