Principal Design Verification Specialist

Job Summary

We are looking for an experienced Design Verification Engineer to join our VLSI team in Bangalore. The ideal candidate will have strong hands-on experience in SystemVerilog, UVM, and verification of complex SoC/IP designs.

Key Responsibilities

• Develop and execute verification plans for IP/SoC level designs
• Build and maintain SystemVerilog/UVM-based verification environments
• Create test scenarios, sequences, scoreboards, and functional coverage models
• Debug and analyze simulation failures;
  work closely with design engineers to resolve issues
• Perform coverage analysis (functional & code coverage) and drive closure
• Review design specifications and ensure verification completeness
• Support regression runs and automation
• Participate in design and verification reviews