Principal Engineer

Description

*ASIC/Processor Design Verification position

*Own all aspects of block/sub-system design-verification:

*test-plan creation/execution

*test-bench (all components) creation/enhancement/maintenance

*code/functional coverage

* Will be involved/interact with: post silicon validation/bring up/emulation teams

Job Requirements:

* Strong expertise in building test-benches using: System-Verilog, UVM, C/C++
* Strong digital logic fundamentals and understanding

* Experience in functional coverage/code coverage/assertions (SVA) development and closure

* Experience in creating and maintaining *executable* test plans
* Strong debug skills
* Proficient in scripting/automation using any standard scripting language like Python etc.

* Emulation related experience will be a plus
* Excellent verbal and written communication skills and a good team player

We’re do...