Job Description

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Our vision is to transform how the world uses information to enrich life.

Join an inclusive team focused on one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solution we create help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while contributing to integrity, sustainability, and giving back to our communities. Because doing so can spark the very innovation we are pursuing.


Job Description:

As a CAD Applications Engineer at Micron Technology, Inc., you will be working in a collaborative, production support role evaluating, improving EDA and debugging both in-house and commercial Electronic Design Automation (EDA) tools and design flows for RTL2GDS methodologies. You will work closely with the Design teams to increase their productivity and work efficiency.

Responsibilities and Tasks include, but not limited to:

Desired candidate should have a good understanding on RTL2GDS flows and methodologies. As CAD engineer he/she should have deeper understanding on how to deliver flows to design teams that enable RTL2GDS flows.

Deliver methodology and tool solutions for static timing closure and power optimization . Deploy innovative modeling and optimization approaches to achieve globally optimal targets .Prudently apply best-in-class algorithms and ECO techniques for value-adding design solutions . Pursue deep analysis of timing paths and power inefficiencies to isolate key issues . Implement code infrastructure to facilitate analytics and visualization . Collaborate with silicon design, CAD, and EDA partners to identify flow deficiencies and enact creative remedies

Qualifications:

  • Typically requires 10+ years of hands on experience in static timing analysis or PNR or RTL2GDS methodologies.
  • Familiar with STA or PNR or Synthesis of large high-performance in Memory technologies
  • Strong analytical skills and ability to identify high ROI opportunities.
  • Proven software engineering background and experience with C++, Python, Tcl programming languages.
  • Solid understanding of cross-talk, variation, and margining.
  • Good communicator who can accurately assess, describe issues to management and follow solutions through to completion.
  • Familiarity with timing and power ECO techniques and implementation is a plus
  • Familiarity with TSMC based designs will be an added plus
  • Leading IP delivery project will be a additional plus

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