Job Description

Job Overview


As a Principal Mask Design Engineer at Tevega Semi, you will be the technical authority for the physical implementation of our most critical analog and mixed-signal IPs. Your primary focus will be the layout of high-current, high-efficiency Voltage Regulator (VR) systems, including Integrated VR (IVR), VR Chiplets, and MBVR (Multi-Bridge Voltage Regulators). You will lead the transition from schematic to silicon, ensuring that layout parasitics and thermal constraints do not compromise the performance of 2026-era high-density power solutions.


Location: Bangalore, India

Experience: 12-15+ years


Key Responsibilities

  • Strategic Layout Leadership: Drive the physical implementation strategy for complex VR IPs, ensuring optimal floorplanning for high-cur...

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