Job Description
Job Overview
As a Principal Mask Design Engineer at Tevega Semi, you will be the technical authority for the physical implementation of our most critical analog and mixed-signal IPs. Your primary focus will be the layout of high-current, high-efficiency Voltage Regulator (VR) systems, including Integrated VR (IVR), VR Chiplets, and MBVR (Multi-Bridge Voltage Regulators). You will lead the transition from schematic to silicon, ensuring that layout parasitics and thermal constraints do not compromise the performance of 2026-era high-density power solutions.
Location: Bangalore, India
Experience: 12-15+ years
Key Responsibilities
- Strategic Layout Leadership: Drive the physical implementation strategy for complex VR IPs, ensuring optimal floorplanning for high-current paths and sensitive control signals.
- Specialized VR Layout: Execute and oversee the layout of Integrated VR (IVR) and MBVR blocks, with specific focus on minimizing, optimizing power-stage efficiency, and managing electromigration (EM) in high-density Fin FET nodes.
- Chiplet & Advanced Packaging: Lead the layout efforts for VR Chiplets, including the design of high-density micro-bumps, interposer routing interfaces, and TSV (Through-Silicon Via) integration.
- Precision Matching: Implement advanced matching techniques for critical analog blocks such as bandgap references, error amplifiers, and high-speed comparators.
- Physical Verification: Drive full-chip and block-level verification including DRC, LVS, ERC, and ANT, with a rigorous focus on EMIR (Electromigration and IR Drop) analysis.
- Top-Level Integration: Manage the integration of digital control logic with analog power stages, ensuring robust shielding and isolation to prevent noise coupling.
- Mentorship & Flow Automation: Establish best practices for mask design within the company and identify opportunities for flow automation using SKILL, Python, or Tcl.
Required Skills & Qualifications
- Education: BE/BTech/ME/MTech/Ph D in Electrical/Electronics Engineering.
- Experience: 12–15+ years of experience in high-performance Analog/Mixed-Signal mask design.
Core Competency – Power & VR:
- Proven expertise in laying out high-current power stages and multi-phase switching regulators.
- In-depth understanding of Integrated VR and MBVR layout challenges (e.g., thermal gradients, parasitics in the power delivery network).
- Experience with Chiplet physical design and 2.5 D/3 D packaging constraints.
Technical Proficiency:
- Expert-level mastery of Cadence Virtuoso (VXL) and Calibre (DRC/LVS/PEX).
- Extensive experience with sub-7nm Fin FET nodes (5nm, 3nm, or 2nm).
- Strong understanding of ESD, LU (Latch-up), and antenna rules in advanced processes.
- Soft Skills: Ability to collaborate closely with Analog Design Engineers to resolve complex trade-offs between area, performance, and reliability.
Please reach out to
As a Principal Mask Design Engineer at Tevega Semi, you will be the technical authority for the physical implementation of our most critical analog and mixed-signal IPs. Your primary focus will be the layout of high-current, high-efficiency Voltage Regulator (VR) systems, including Integrated VR (IVR), VR Chiplets, and MBVR (Multi-Bridge Voltage Regulators). You will lead the transition from schematic to silicon, ensuring that layout parasitics and thermal constraints do not compromise the performance of 2026-era high-density power solutions.
Location: Bangalore, India
Experience: 12-15+ years
Key Responsibilities
- Strategic Layout Leadership: Drive the physical implementation strategy for complex VR IPs, ensuring optimal floorplanning for high-current paths and sensitive control signals.
- Specialized VR Layout: Execute and oversee the layout of Integrated VR (IVR) and MBVR blocks, with specific focus on minimizing, optimizing power-stage efficiency, and managing electromigration (EM) in high-density Fin FET nodes.
- Chiplet & Advanced Packaging: Lead the layout efforts for VR Chiplets, including the design of high-density micro-bumps, interposer routing interfaces, and TSV (Through-Silicon Via) integration.
- Precision Matching: Implement advanced matching techniques for critical analog blocks such as bandgap references, error amplifiers, and high-speed comparators.
- Physical Verification: Drive full-chip and block-level verification including DRC, LVS, ERC, and ANT, with a rigorous focus on EMIR (Electromigration and IR Drop) analysis.
- Top-Level Integration: Manage the integration of digital control logic with analog power stages, ensuring robust shielding and isolation to prevent noise coupling.
- Mentorship & Flow Automation: Establish best practices for mask design within the company and identify opportunities for flow automation using SKILL, Python, or Tcl.
Required Skills & Qualifications
- Education: BE/BTech/ME/MTech/Ph D in Electrical/Electronics Engineering.
- Experience: 12–15+ years of experience in high-performance Analog/Mixed-Signal mask design.
Core Competency – Power & VR:
- Proven expertise in laying out high-current power stages and multi-phase switching regulators.
- In-depth understanding of Integrated VR and MBVR layout challenges (e.g., thermal gradients, parasitics in the power delivery network).
- Experience with Chiplet physical design and 2.5 D/3 D packaging constraints.
Technical Proficiency:
- Expert-level mastery of Cadence Virtuoso (VXL) and Calibre (DRC/LVS/PEX).
- Extensive experience with sub-7nm Fin FET nodes (5nm, 3nm, or 2nm).
- Strong understanding of ESD, LU (Latch-up), and antenna rules in advanced processes.
- Soft Skills: Ability to collaborate closely with Analog Design Engineers to resolve complex trade-offs between area, performance, and reliability.
Please reach out to
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