Job Description
Responsibilities
Maxlinear is seeking a Principal Physical Design Engineer (SoC Middle-End - RTL2NETLIST) to join our team in Singapore. Be part of a SoC LPS team dealing with complex Communication ICs (wifi, router, ethernet ) in 7nm and below and focusing on:
Perform Design synthesis with Synopsys/Cadence toolset, with full knowledge and understanding of functional constraints Create timing constraints for functional, DFT modes for synthesis/STA by working closely with Design and DFT Engineers STA/timing closure Write Low power intent file (CPF/UPF) from specification and verifying correctness of power intent file using CLP/VCLP Perform Logic equivalence checks Work with physical design engineer to resolve all netlist and timing issues
Qualifications
Master's/Bachelor's Degree in Electrical/Electronics Engineering with an emphasis in IC design Good experience wit...
Apply for this Position
Ready to join MaxLinear? Click the button below to submit your application.
Submit Application