Principal STA/Synthesis Engineer

Job Descriptions & Requirements

Part of the rapidly expanding Hardware-Analytics and Test (HAT) business unit, an STA expert works on the development of various SLM IPs and subsystems as part of SHG (SLM Hardware Group) product portfolio. As a lead STA engineer, you will be part of our Design team developing state-of-the-art SLM Controllers, on-chip Monitors and Infrastructure IPs, on most advanced process nodes (from 16nm down to 3nm and beyond). We are seeking an experienced, highly motivated and high-caliber individual to build these differentiating products. This individual should have strong technical experience in static-timing analysis, place & route, backend implementation, signoff while possessing excellent project execution and planning skills.

Job Requirements

• Strong experience in STA concepts, tools and methodologies at IP/subsystem/chip levels
• Sound knowledge of standard ASIC RTL2GDS physical implementation and signoff flows
• Ability to understand IP/subsystem design and come up with STA plan/checkers and reviews
• Hands-on experience in Synthesis, pre-layout STA, post-layout STA, CTS tools
• BS or MS degree in Electrical Engineering with 8+ years of relevant industry experience
• Exposure to design implementation and signoff of soft & mixed-signal IPs and subsystems
• Excellent teamwork, communication, mentoring and interpersonal skills with both internal teams and external customers

Preferred skills :

• 12+ Years of relevant experience
• Strong pre & post layout STA and signoff experience, including SDC development, multi-mode design development experience
• Mandatory experience in Functional, DFT (scan-shift, scan-capture and at-speed) mode constraints development and timing closure with MCMM (multi-corner, multi-mode)
• Strong understanding of RTL2GDSII flow and design implementation methodologies such as synthesis, place & route, timing closure, STA, EMIR, and layout closure
• Proficiency with BE & STA tools from any EDA vendor, preferably Synopsys tools like PrimeTime, ICC2, Design Compiler, Fusion Compiler (or equivalent) used in the RTL2GDSII implementation
• Proven track record of successful timing closure & tape-outs in advanced nodes (14nm, 10nm, 7nm, 5nm, 3nm, 2nm etc...)
• Good understanding of OCV, POCV, derates, crosstalk and design margins
• Experience with design methodologies like developing custom scripts and enhancing flows for better execution. Experience in scripting with TCL/PERL is required
• Understanding of RTL2GDSII flow and design implementation methodologies such as synthesis, place & route, timing closure, STA, EMIR, and layout closure
• Good communication skills, and ability to work in a global environment