Job Description
TITLE: DIGITAL DESIGN ENGINEER(SENIOR PRINCIPAL/PRINCIPAL) LOCATION: GREATER BENGALURU AREA
Company Description
We are NASDAQ Listed Organization and we provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, we enable organizations to unlock the full potential of modern AI. Our Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
Job Description
Senior Principal/Principal Digital Design Engineer
We are seeking a Principal Digital Design Engineer with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions.
Key Responsibilities
Design and implement high-performance digital solutions, including RTL development and synthesis.
Collaborate with cross-functional teams on IP integration for processor IPS and peripherals
Deep knowledge of processor boot process and peripheral implementation with boot firmware in mind
Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm.
Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug.
Utilize tools from Synopsys/Cadence and apply expertise in UVM-based verification flows
Basic Qualifications
Bachelor’s in Electronics/Electrical engineering (Master's preferred).
10-20 years of digital design experience, with 4+ years focused on processor, peripherals and full chip implementation.
Proven expertise in RTL development, synthesis, and timing closure.
Experience with front-end design, gate-level simulations, and design verification.
Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude.
Required Expertise
Hands-on experience with processor IP (ARM/ARC)
Hands-on pre-silicon and post-silicon implementing peripherals for I2C/SPI/UART
Hands-on experience with complex DMA engines and FW interaction
Strong proficiency in System Verilog/Verilog and scripting (Python/Perl).
Experience with block-level and full-chip design at advanced nodes (≤ 16nm).
Silicon bring-up and post-silicon debug experience.
Familiarity with Synopsys/Cadence tools and UVM-based design verification.
Preferred Experience
Knowledge and experience implementing secure boot and security mechanisms like authentication and attestation is a plus
Knowledge of system-level design with ARM/ARC/RISC-V processors sub systems
Understanding of PAD design, DFT, and floor planning.
Experience with NIC, switch, or storage product development.
Familiarity with working in design and verification workflows in a CI/CD environment.
Contact
Sumit S. B
[email protected]
"Mining the Knowledge Community"
Practice Head(Talent Acquisition. Semiconductors Domain)
Company Description
We are NASDAQ Listed Organization and we provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, we enable organizations to unlock the full potential of modern AI. Our Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
Job Description
Senior Principal/Principal Digital Design Engineer
We are seeking a Principal Digital Design Engineer with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions.
Key Responsibilities
Design and implement high-performance digital solutions, including RTL development and synthesis.
Collaborate with cross-functional teams on IP integration for processor IPS and peripherals
Deep knowledge of processor boot process and peripheral implementation with boot firmware in mind
Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm.
Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug.
Utilize tools from Synopsys/Cadence and apply expertise in UVM-based verification flows
Basic Qualifications
Bachelor’s in Electronics/Electrical engineering (Master's preferred).
10-20 years of digital design experience, with 4+ years focused on processor, peripherals and full chip implementation.
Proven expertise in RTL development, synthesis, and timing closure.
Experience with front-end design, gate-level simulations, and design verification.
Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude.
Required Expertise
Hands-on experience with processor IP (ARM/ARC)
Hands-on pre-silicon and post-silicon implementing peripherals for I2C/SPI/UART
Hands-on experience with complex DMA engines and FW interaction
Strong proficiency in System Verilog/Verilog and scripting (Python/Perl).
Experience with block-level and full-chip design at advanced nodes (≤ 16nm).
Silicon bring-up and post-silicon debug experience.
Familiarity with Synopsys/Cadence tools and UVM-based design verification.
Preferred Experience
Knowledge and experience implementing secure boot and security mechanisms like authentication and attestation is a plus
Knowledge of system-level design with ARM/ARC/RISC-V processors sub systems
Understanding of PAD design, DFT, and floor planning.
Experience with NIC, switch, or storage product development.
Familiarity with working in design and verification workflows in a CI/CD environment.
Contact
Sumit S. B
[email protected]
"Mining the Knowledge Community"
Practice Head(Talent Acquisition. Semiconductors Domain)
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