Job Description
Benchmarking, Travel – as necessary
ESSENTIAL ATTRIBUTES:
Ability to manage, mentor, and lead a team of highly motivated professionals.
Able to work independently, self-motivated with a strong drive to win.
Team player with the ability to work across diverse cross-functional teams spread across the world.
Leadership skills to influence all levels of the organization.
You’re inclusive, adapting your style to the situation and diverse global norms of our people.
An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
Innovative and creative, you proactively explore new ideas and adapt quickly to change.
Tier-1 Execution Mindset: Deep understanding of what constitutes production-worthy technology at leading foundries.
Integrity & Trust: Demonstrates mission-driven leadership with strong ownership and accountability.
QUALIFICATIONS:
M. S. or Ph. D. in Electrical Engineering, Materials Science, Engineering Physics, Chemical Engineering, or a related field.
Deep expertise in CMOS technology integration, including device physics and process interactions. Has directly worked on planar HKMG structures, Si Ge stressors, BEOL integration schemes, etc at 2 X nodes
Strong working knowledge of SRAM, logic, RF, power devices, and e NVM integration considerations; experience in achieving competitive performance
Proven capability to guide TCAD, compact modeling, and variability modeling teams to align prediction with silicon.
Advanced understanding of failure mechanisms, reliability physics, and analytical techniques.
Demonstrated success managing large, complex R&D programs with tight timelines and business impact.
Strong understanding of device physics, process modules, yield improvement, failure mechanisms, analytical techniques (physical and electrical)
Proven track record in developing and transferring technologies into high volume manufacturing
Can guide team to design and layout E-test structures and analyze/interpret data from these structures
Familiarity with Finfet structures
Ability to lead cross-functional teams and achieve project completion within timeline and cost targets
Ability to work across different cultures and geographies
Innovation mindset
DESIRED EXPERIENCE:
15+ years of semiconductor industry experience.
Significant tenure in a Tier-1 foundry or leading IDM environment.
Proven track record of: Technology transfer , Yield ramp to HVM , Post-transfer performance enhancement, and developing new technologies into high volume production
Experience with 22nm / 28nm nodes is required; Fin FET experience is strongly preferred.
Prior leadership at Director / Sr. Director / AVP level with responsibility for large technical organizations.
ESSENTIAL ATTRIBUTES:
Ability to manage, mentor, and lead a team of highly motivated professionals.
Able to work independently, self-motivated with a strong drive to win.
Team player with the ability to work across diverse cross-functional teams spread across the world.
Leadership skills to influence all levels of the organization.
You’re inclusive, adapting your style to the situation and diverse global norms of our people.
An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
Innovative and creative, you proactively explore new ideas and adapt quickly to change.
Tier-1 Execution Mindset: Deep understanding of what constitutes production-worthy technology at leading foundries.
Integrity & Trust: Demonstrates mission-driven leadership with strong ownership and accountability.
QUALIFICATIONS:
M. S. or Ph. D. in Electrical Engineering, Materials Science, Engineering Physics, Chemical Engineering, or a related field.
Deep expertise in CMOS technology integration, including device physics and process interactions. Has directly worked on planar HKMG structures, Si Ge stressors, BEOL integration schemes, etc at 2 X nodes
Strong working knowledge of SRAM, logic, RF, power devices, and e NVM integration considerations; experience in achieving competitive performance
Proven capability to guide TCAD, compact modeling, and variability modeling teams to align prediction with silicon.
Advanced understanding of failure mechanisms, reliability physics, and analytical techniques.
Demonstrated success managing large, complex R&D programs with tight timelines and business impact.
Strong understanding of device physics, process modules, yield improvement, failure mechanisms, analytical techniques (physical and electrical)
Proven track record in developing and transferring technologies into high volume manufacturing
Can guide team to design and layout E-test structures and analyze/interpret data from these structures
Familiarity with Finfet structures
Ability to lead cross-functional teams and achieve project completion within timeline and cost targets
Ability to work across different cultures and geographies
Innovation mindset
DESIRED EXPERIENCE:
15+ years of semiconductor industry experience.
Significant tenure in a Tier-1 foundry or leading IDM environment.
Proven track record of: Technology transfer , Yield ramp to HVM , Post-transfer performance enhancement, and developing new technologies into high volume production
Experience with 22nm / 28nm nodes is required; Fin FET experience is strongly preferred.
Prior leadership at Director / Sr. Director / AVP level with responsibility for large technical organizations.
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