Job Description
RTL Design Engineer (SDC Constraints)
๐๐ ๐ฝ๐ฒ๐ฟ๐ถ๐ฒ๐ป๐ฐ๐ฒ: ๐ณ+ ๐ฌ๐ฒ๐ฎ๐ฟ๐
๐๐ผ๐ฐ๐ฎ๐๐ถ๐ผ๐ป: ๐๐ฎ๐ป๐ด๐ฎ๐น๐ผ๐ฟ๐ฒ
๐ช๐ผ๐ฟ๐ธ ๐ ๐ผ๐ฑ๐ฒ: ๐๐๐ฏ๐ฟ๐ถ๐ฑ / ๐ฅ๐ฒ๐บ๐ผ๐๐ฒ
๐๐ผ๐ฏ ๐ข๐๐ฒ๐ฟ๐๐ถ๐ฒ๐
We are looking for a highly skilled Senior RTL ASIC Design Engineer with strong hands-on experience in SDC Constraints. The ideal candidate will have deep expertise in RTL design, timing constraints, and close collaboration with synthesis and STA teams.
๐๐ฒ๐ ๐ฅ๐ฒ๐๐ฝ๐ผ๐ป๐๐ถ๐ฏ๐ถ๐น๐ถ๐๐ถ๐ฒ๐
Design and develop RTL (Verilog/SystemVerilog) for complex ASIC blocks and subsystems
Create, review, and maintain SDC constraints (clock definitions, I/O constraints, false paths, multicycle paths, exceptions, etc.)
Work closely with synthesis, STA, physical design, and verification teams to achieve timing closure
Perform RTL quality checks, linting, and CDC analysis
Support timing debugging and constraint optimization across multiple design iterations
Participate in architecture discussions and design reviews
Ensure deliverables meet performance, power, and a...
๐๐ ๐ฝ๐ฒ๐ฟ๐ถ๐ฒ๐ป๐ฐ๐ฒ: ๐ณ+ ๐ฌ๐ฒ๐ฎ๐ฟ๐
๐๐ผ๐ฐ๐ฎ๐๐ถ๐ผ๐ป: ๐๐ฎ๐ป๐ด๐ฎ๐น๐ผ๐ฟ๐ฒ
๐ช๐ผ๐ฟ๐ธ ๐ ๐ผ๐ฑ๐ฒ: ๐๐๐ฏ๐ฟ๐ถ๐ฑ / ๐ฅ๐ฒ๐บ๐ผ๐๐ฒ
๐๐ผ๐ฏ ๐ข๐๐ฒ๐ฟ๐๐ถ๐ฒ๐
We are looking for a highly skilled Senior RTL ASIC Design Engineer with strong hands-on experience in SDC Constraints. The ideal candidate will have deep expertise in RTL design, timing constraints, and close collaboration with synthesis and STA teams.
๐๐ฒ๐ ๐ฅ๐ฒ๐๐ฝ๐ผ๐ป๐๐ถ๐ฏ๐ถ๐น๐ถ๐๐ถ๐ฒ๐
Design and develop RTL (Verilog/SystemVerilog) for complex ASIC blocks and subsystems
Create, review, and maintain SDC constraints (clock definitions, I/O constraints, false paths, multicycle paths, exceptions, etc.)
Work closely with synthesis, STA, physical design, and verification teams to achieve timing closure
Perform RTL quality checks, linting, and CDC analysis
Support timing debugging and constraint optimization across multiple design iterations
Participate in architecture discussions and design reviews
Ensure deliverables meet performance, power, and a...
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