Job Description
Role: RTL Designer
Experience: 4 – 8 Years
Location : Bangalore & Hyderabad
Job Description
- So C / IP RTL Design Engineer with 4 – 8 years’ experience
- Expertise in writing RTL in Verilog and System Verilog
- Hands-on experience in design static checks like Lint, CDC, RDC, CLP, UPF
- Hands-on experience in integration of IP, chip IO integration
- Any candidate with PCIE/USB/Ethernet experience is good.
- Working knowledge of GIT is preferred
- Excellent analytical, and problem-solving skills
- Should have good understanding of So C design flows
Experience: 4 – 8 Years
Location : Bangalore & Hyderabad
Job Description
- So C / IP RTL Design Engineer with 4 – 8 years’ experience
- Expertise in writing RTL in Verilog and System Verilog
- Hands-on experience in design static checks like Lint, CDC, RDC, CLP, UPF
- Hands-on experience in integration of IP, chip IO integration
- Any candidate with PCIE/USB/Ethernet experience is good.
- Working knowledge of GIT is preferred
- Excellent analytical, and problem-solving skills
- Should have good understanding of So C design flows
Apply for this Position
Ready to join ? Click the button below to submit your application.
Submit Application