RTL Design Engineer (ASIC RTL)

Experience: 5–10 years only

Client: Proxelera ODC – Edge AI Video Processing Chip

This role is for engineers who live inside RTL, not around it.You will design real ASIC blocks that ship, not glue logic that gets forgotten. If micro-architecture to clean, timing-aware RTL is your comfort zone, this is your lane.

Work

• Own block-level RTL development in Verilog/SystemVerilog for ASIC designs

• Convert micro-architecture into synthesizable RTL with focus on area, latency, and power

• Design FSMs, pipelines, and datapaths used in production silicon

• Run and clean up CDC, Lint, and X-prop checks

• Collaborate closely with DV and synthesis teams to close design issues

Must-Have Experience

• Strong ASIC RTL coding experience (integration-only profiles will be rejected)

• Multiple ASIC RTL development projects end-to-end

• Hands-on CDC, Lint, X-prop cleanup

• FPGA-only experience will be discounted

• Synthesis or constraint knowledge is a plus, not mandatory

Cheers,

Shahid