Job Description
TITILE: RTL DESIGN ENGINEER (Principal/Senior Staff/Staff Engineer)
Location: Bangalore/Hyderabad
EXPERIENCE: 10 years to 15 years
RTL design in Verilog/SystemVerilog
Skills Required
systemverilog
Location: Bangalore/Hyderabad
EXPERIENCE: 10 years to 15 years
RTL design in Verilog/SystemVerilog
- Micro-architecture, integration & debug
- Synthesis-friendly coding practices
- Experience in ASIC SoC designs
- RTL design in Verilog/SystemVerilog
- Micro-architecture, integration & debug
- Synthesis-friendly coding practices
- Experience in ASIC SoC designs
Skills Required
systemverilog
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