RTL Design Engineer

<p style="margin-bottom:11px">Experience - 5- 10 years </p> <p style="margin-bottom:11px">No of postion-1</p> <p style="margin-bottom:11px">Work location bangalore </p> <p style="margin-bottom:11px"> </p> <p style="margin-bottom:11px">Job Description:</p> <ul> <li style="margin-bottom:11px">Experience in coding RTL blocks and/or algorithms for ASICs in Verilog/SV in at least 2 projects is mandatory. This candidate could also have worked on a few RTL integration projects, but at least 2 RTL development (coding) projects are needed.</li> <li style="margin-bottom:11px">Experience in running QC checks (CDC, Lint, X-prop) on the design and cleaning up design issues is mandatory</li> <li style="margin-bottom:11px">One or two FPGA RTL projects are OK, but the remaining projects must be ASIC RTL projects</li> <li style="margin-bottom:11px">Synthesis and constraint writing experience is good to have, but not mandatory</li> </ul>