Job Description
RTL Design Engineer, Cloud TPU
_corporate_fare_ Google _place_ Sunnyvale, CA, USA
**Early**
Experience completing work as directed, and collaborating with teammates; developing knowledge of relevant concepts and processes.
**Minimum qualifications:**
+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience.
+ Experience in ASIC RTL design using systemverilog or verilog.
+ Experience in scripting (e.g., Python, Tcl, or Perl) and debugging with tools like Verdi or VCS.
+ Experience with soc bus protocols (e.g., APB, AHB, or AXI) and register-mapped architectures.
**Preferred qualifications:**
+ Master's degree or PhD in Electrical Engineering or Computer Engineering, with an emphasis on computer architecture.
+ 2 years of experience in ASIC design, specifically designing management and controllability subsystems or SoC chas...
_corporate_fare_ Google _place_ Sunnyvale, CA, USA
**Early**
Experience completing work as directed, and collaborating with teammates; developing knowledge of relevant concepts and processes.
**Minimum qualifications:**
+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience.
+ Experience in ASIC RTL design using systemverilog or verilog.
+ Experience in scripting (e.g., Python, Tcl, or Perl) and debugging with tools like Verdi or VCS.
+ Experience with soc bus protocols (e.g., APB, AHB, or AXI) and register-mapped architectures.
**Preferred qualifications:**
+ Master's degree or PhD in Electrical Engineering or Computer Engineering, with an emphasis on computer architecture.
+ 2 years of experience in ASIC design, specifically designing management and controllability subsystems or SoC chas...
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