Job Description

  • Leading design, micro-architecture and integration of the System on Chip (SOC) from initial specification till tape out and beyond
  • Drive and implement best SoC design methodology/practices and scale it across different business lines.
  • Signing off RTL, timing constraints, CDC, RDC and work with different functions like verification, DFT, synthesis, etc. to get to a production quality Silicon.
  • Documenting the SOC design and micro-architecture for usage by other SOC functions
  • Provide design support for any silicon related debugs of chips in post-silicon phase
  • ASIC designers and Design Leads with experiences in all aspects of RTL design flow from Specification/Micro-architecture definition to design and verification, Timing Analysis, DFT and Implementation.
  • Good knowledge of Digital Design and hands-on experience with Verilog RTL coding
  • Should have a firm understanding and hands-on experience on Chip Assembly, IP Integration, RTL signoff tools and CDC/RDC/Lint/Synthesis.
  • Familiarity with Computer architecture: knowledge of microprocessors (ARM, RISC-V), bus protocols preferred (AXI/ACE/APB/ATB). Knowledge on CPU architecture, coherency protocols, Virtualization, Core-sight and peripherals like PCIe, USB, DDRs is highly desirable.
  • Strong domain knowledge of Clocking, Reset, System modes, Power management, debug, interconnect, safety, security and other architectures Know-how of Serial Interfaces, Multimedia, External Bus Interfaces, ISO26262 based functional safety relevant microprocessor architectures is preferred.
  • Self-motivated to drive issues to closure. Should be a team player and willing to work with cross functional teams on issues resolution.
  • Excellent written and verbal communication skill.
  • Creative problem-solving skills, logic analysis skills, ability to logically break complex problems down to manageable components.

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