RTL Design Engineer - Intermediate (US)

Hands-on RTL design and development using SystemVerilog / Verilog FPGA-based design including simulation, synthesis, and implementation Strong experience with Xilinx/AMD Vivado tool flow Integration of high-speed interfaces such as PCIe, DDR, Ethernet, and AXI Pre-silicon verification and post-silicon validation/debug TCL and Python scripting for automation and build flows